Diachenko Yuri Georgievich

Publications in Math-Net.Ru

1. Multioption redundancy taking into account logical and topological features of transistor circuit
   
   Inform. Primen., 19:3 (2025),  55–66
2. Template method in synthesis of self-timed digital circuits
   
   Sistemy i Sredstva Inform., 35:4 (2025),  4–19
3. Implementation of synchronous flip-flop and latch functionality in a self-timed basis
   
   Sistemy i Sredstva Inform., 35:3 (2025),  3–16
4. Combined encoding in elements of field-programmable gate arrays
   
   Sistemy i Sredstva Inform., 35:2 (2025),  3–16
5. Properties and optimization of self-timed circuits
   
   Sistemy i Sredstva Inform., 35:1 (2025),  149–169
6. A new approach to implementing logical functions in field-programmable gate arrays
   
   Sistemy i Sredstva Inform., 34:4 (2024),  3–15
7. Self-timed up counter implementation
   
   Sistemy i Sredstva Inform., 34:3 (2024),  123–135
8. Self-timed counter synthesis formalization
   
   Sistemy i Sredstva Inform., 34:2 (2024),  66–82
9. Desynchronization methodology at self-timed circuit synthesis
   
   Sistemy i Sredstva Inform., 34:1 (2024),  33–43
10. Replacing synchronous triggers with self-timed counterparts during circuit desynchronization
    
    Sistemy i Sredstva Inform., 33:4 (2023),  4–15
11. Multiplexed self-timed pipeline
    
    Sistemy i Sredstva Inform., 33:2 (2023),  4–12
12. Self-timed pipeline with variable stage number
    
    Sistemy i Sredstva Inform., 33:1 (2023),  4–13
13. Approximate evaluation of the efficiency of synchronous and self-timed methodologies in problems of designing failure-tolerant computing and control systems
    
    Avtomat. i Telemekh., 2022, no. 2,  122–132
14. Synchronous and self-timed pipeline's reliability estimation
    
    Inform. Primen., 16:4 (2022),  2–7
15. Self-timed pipeline's soft error tolerance analysis
    
    Sistemy i Sredstva Inform., 32:4 (2022),  4–13
16. Self-timed shift register cases
    
    Sistemy i Sredstva Inform., 32:3 (2022),  81–91
17. The electronic component base of failure resilience digital circuits
    
    Inform. Primen., 15:4 (2021),  65–71
18. Hardware support of fast Fourier transform optimization in a recurrent signal processor
    
    Sistemy i Sredstva Inform., 31:4 (2021),  71–83
19. Recurrent signal processor hardware implementation
    
    Sistemy i Sredstva Inform., 31:3 (2021),  113–122
20. Improvement of self-time circuit soft error tilerance
    
    Inform. Primen., 14:4 (2020),  63–68
21. Multicore hybrid recurrent architecture expansion on FPGA
    
    Sistemy i Sredstva Inform., 30:4 (2020),  95–101
22. Self-timed pipeline immunity to soft errors in its combinational part
    
    Sistemy i Sredstva Inform., 30:3 (2020),  49–55
23. Self-timed combinational circuit tolerance to short-term soft errors
    
    Sistemy i Sredstva Inform., 30:2 (2020),  4–10
24. Indication optimization in multibit self-timed circuits
    
    Sistemy i Sredstva Inform., 29:4 (2019),  14–27
25. Sequential self-timed cell characterization
    
    Sistemy i Sredstva Inform., 29:3 (2019),  104–113
26. Fault-tolerant self-timed serial-parallel port: variants of realization
    
    Sistemy i Sredstva Inform., 26:3 (2016),  48–59
27. Hardware and software modeling and testing of the recurrent operational device
    
    Sistemy i Sredstva Inform., 25:4 (2015),  78–90
28. Implementation basis of exaflops class supercomputer
    
    Inform. Primen., 8:1 (2014),  45–70
29. Self-timed fused multiply-add unit: Practical implementation
    
    Sistemy i Sredstva Inform., 24:3 (2014),  63–77
30. Fused multiply-add: Methodological aspects
    
    Sistemy i Sredstva Inform., 24:3 (2014),  44–62
31. Tools for self-timed cells characterization
    
    Sistemy i Sredstva Inform., 22:1 (2012),  38–48
32. Self-timed analysis of some types of digital device
    
    Sistemy i Sredstva Inform., 21:1 (2011),  74–83
33. Designing of the delay-independent computing device
    
    Sistemy i Sredstva Inform., 20:1 (2010),  5–23
34. Quasi self-timed realization of the device for division and square-root generation
    
    Sistemy i Sredstva Inform., 2008, no. 18,  234–260
35. Self-timed sequential circuits: Development experience and design guideline
    
    Sistemy i Sredstva Inform., 2007, no. 17,  503–529