Zolotorevich Ludmila A

Publications in Math-Net.Ru

1. Project verification and construction of superchip tests at the RTL level
   
   Avtomat. i Telemekh., 2013, no. 1,  146–158
2. Development of tests for VLSI circuit testability at the upper design levels
   
   Avtomat. i Telemekh., 2010, no. 9,  162–173
3. Switch-level VLSI quasistatic simulation methods: comparative accuracy of models
   
   Avtomat. i Telemekh., 1998, no. 9,  130–141
4. Switching Modelling and Testing of MOP-Structures
   
   Avtomat. i Telemekh., 1992, no. 11,  133–144