Diachenko Denis Yur'evich

Publications in Math-Net.Ru

1. Implementation of synchronous flip-flop and latch functionality in a self-timed basis
   
   Sistemy i Sredstva Inform., 35:3 (2025),  3–16
2. Self-timed up counter implementation
   
   Sistemy i Sredstva Inform., 34:3 (2024),  123–135
3. Self-timed counter synthesis formalization
   
   Sistemy i Sredstva Inform., 34:2 (2024),  66–82
4. Multiplexed self-timed pipeline
   
   Sistemy i Sredstva Inform., 33:2 (2023),  4–12
5. Self-timed pipeline with variable stage number
   
   Sistemy i Sredstva Inform., 33:1 (2023),  4–13
6. Self-timed pipeline's soft error tolerance analysis
   
   Sistemy i Sredstva Inform., 32:4 (2022),  4–13
7. Self-timed shift register cases
   
   Sistemy i Sredstva Inform., 32:3 (2022),  81–91
8. Self-timed pipeline immunity to soft errors in its combinational part
   
   Sistemy i Sredstva Inform., 30:3 (2020),  49–55
9. Self-timed combinational circuit tolerance to short-term soft errors
   
   Sistemy i Sredstva Inform., 30:2 (2020),  4–10
10. Indication optimization in multibit self-timed circuits
    
    Sistemy i Sredstva Inform., 29:4 (2019),  14–27
11. Sequential self-timed cell characterization
    
    Sistemy i Sredstva Inform., 29:3 (2019),  104–113