Hardware acceleration of Qemu MMU for aarch64 on x86-64 full system emulation

D. N. Poletaev^ab, P. M. Dovgalyuk^ab, G. N. Teys^ab, M. A. Kostin<sup>ab

a</sup> Ivannikov Institute for System Programming of the RAS
^b Yaroslav-the-Wise Novgorod State University

Abstract: Full system cross-ISA emulation is widely used nowdays, but is known for being slow. Major contribution to the slowdown is made by software MMU doing guest virtual addresses translation. In article we look at optimization which allows to move part of such address translation work to the hardware MMU of the host system. For this goal, extra view to the whole guest virtual address space is added to the address space of the emulator process, using mmap system call. After mapping is done there is opportunity to use fixed offset correction to guest virtual address in the translated binary code in place of dynamic search of needed offset in software TLB. Additional view of guest virtual address space maintained coherent with guest page tables. Such approach allows to use less host instructions per each guest memory instruction, which lead to notable emulation acceleration, considering the large quantity of memory instructions in the guest execution flow. Measurments show speed up as large as 271

Keywords: virtual machines, full system emulation, hardware MMU, emulation speed up

DOI: 10.15514/ISPRAS-2025-37(6)-35