Abstract:
The article considers the problem of self-timed (ST) digital circuit design automation. Self-timed circuits are an alternative to the synchronous ones. In spite of significant advantages, especially in terms of operational reliability in a wide range of operating conditions under the influence of unfavorable factors, ST circuits have not yet found wide application. In part, this is due to the complexity of their design which requires a specific approach and consideration of the ST circuit's functioning discipline features. The greatest difficulty is the formalization and automation of sequential ST unit synthesis. For this purpose, it is proposed to use the template method. It includes an analysis of the synchronous counterpart's original description of the synthesized ST circuit using Yosys, the open-source logical synthesizer of synchronous circuits, searching for fragments implemented by units with memory, and replacing them with pre-prepared templates, namely, ST Verilog descriptions of sequential units adequate to the prototype in terms of operational features. The templates contain the synchronous and ST implementations of the corresponding units. The article provides template examples and describes the method of their application in the process of converting the original synchronous description of the synthesized circuit into an ST Verilog description. Substituting templates into the synthesized circuit description eliminates the need for their individual synthesis taking into account the specifics of the ST circuits. The proposed approach ensures minimal hardware costs and optimal performance and guarantees the ST nature of the resulting circuit implementations of digital units.
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