This article is cited in 1 paper

Implementation of synchronous flip-flop and latch functionality in a self-timed basis

Yu. G. Diachenko, L. P. Plekhanov, N. V. Morozov, D. Yu. Stepchenkov, G. A. Orlov, D. Yu. Diachenko

Federal Research Center "Computer Science and Control" of the Russian Academy of Sciences, 44-2 Vavilov Str., Moscow 119333, Russian Federation

Abstract: The article considers the self-timed (ST) flip-flop development issues based on the original description of their synchronous counterparts functioning at the behavioral level. The options of synchronous flip-flops and their compliance with the ST flip-flop's behavioral features are analyzed. The implementations of some typical ST flip-flops with preset options are represented. A method for converting synchronous flip-flop behavioral description into an ST counterpart taking into account the ST circuit operation specifics is proposed. Asynchronous reset and set of the synchronous flip-flop remain asynchronous in the ST counterpart as well, they are not indicated. Synchronous reset and set are transformed into ST reset and ST set, respectively. Their successful completion is indicated. The paper shows that it is advisable to implement ST reset and ST set by preliminary mixing of reset and set signals with the flip-flop information input. Substitution of the ST flip-flop instead of the synchronous prototype is carried out using templates that ensure the replacement adequacy, the optimality of the hardware implementation, and the self-timing of the resulting circuit.

Keywords: self-timed circuit, flip-flop, Verilog description, operating range, register, element base, robotic system.

Received: 10.04.2025
Accepted: 15.09.2025

DOI: 10.14357/08696527250301