Self-timed up counter implementation

Yu. A. Stepchenkov, Yu. G. Diachenko, N. V. Morozov, D. Yu. Stepchenkov, D. Yu. Diachenko

Federal Research Center "Computer Science and Control" of the Russian Academy of Sciences, 44-2 Vavilov Str., Moscow 119133, Russian Federation

Abstract: The article is devoted to the problem of self-timed (ST) binary up counter implementation. The ST circuits are an alternative to the synchronous ones when implementing digital units. The ST basis ensures stable operation of a digital unit regardless of any delays in the internal logical cells. A two-phase operating discipline and full indication of all circuit's switches provide such behavior but they require some hardware redundancy. In terms of permissible operating conditions including supply voltage and ambient temperature, ST circuits have a significant advantage over synchronous counterparts. Sequential ST counters are less redundant than combinational ST circuits due to the simpler indication subcircuit. Their synthesis is quite simply formalized on the ready-made counting ST flip-flops basis. However, to implement their ST preset, one should perform a certain time sequence of their inputs. The article considers the circuitry basis for the ST up counter implementation and proposes optimal circuitry solutions in terms of hardware complexity that provide ST counter preset.

Keywords: self-timed circuit, binary counter, indication, preset, hardware complexity, performance, self-timed analysis.

Received: 27.04.2024

DOI: 10.14357/08696527240309