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Fizika i Tekhnika Poluprovodnikov, 2024 Volume 58, Issue 3, Pages 149–155 (Mi phts6732)

Semiconductor physics

Research of design and technological features of manufacturing of low-noise GaAs transistors with T-gate length of 150 nm for information transmission systems

A. E. Shesterikov, D. A. Shesterikova, E. V. Erofeev

Tomsk State University of Control Systems and Radioelectronics, 634050 Tomsk, Russia

Abstract: The work presents the results of research of design and technological features of manufacturing of low-noise transistors for information transmission systems. With the software system Synopsys Technology Computer-Aided Design, the optimal parameters of heterostructure layers were determined at mole fraction of indium in the channel equal to 20%, thickness of the barrier layer 18 nm, thickness of the channel layer 12 nm and delta doping concentration 5 $\cdot$ 10$^{12}$ cm$^{-2}$. Research was conducted on the effect of the recess length of the sub-gate region of GaAs transistors on their electrical characteristics. It was found that with the increase of the recess length there is an increase in the gate-to-drain breakdown voltages of the transistor. It is revealed that additional liquid treatment before dielectric deposition decreases the specific drain current density and the transconductance of the volt-ampere characteristic, but allows increasing the gate-drain breakdown voltage of transistors.

Keywords: $p$HEMT, low-noise transistor, gate recess, MMIC, modeling, heterostructure.

Received: 16.01.2024
Revised: 18.04.2024
Accepted: 18.04.2024

DOI: 10.61011/FTP.2024.03.58406.5925



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