Logical Design of Discrete Automata

FPGA implementation of the Kuznyechik cipher in counter mode

S. I. Razenkov


Abstract: A hardware implementation of the block cipher “Kuznyechik” in counter mode has been made. Utilization has been improved by using the structure of the S-transformation, which consists of 4-bit S-boxes, linear permutations and finite field multiplications, and representing the L-transformation as matrix multiplication. These solutions also allow manual pipelining, which can improve throughput. The FPGA implementation using PCI Express 4.0 x8 interface achieved encryption speeds up to 56 Gbit/s and outperforms a software implementation using SIMD instructions which reaches only 1.7 Gbit/s.

Keywords: FPGA, block cipher Kuznyechik, counter mode.

UDC: 004.056.55

DOI: 10.17223/2226308X/18/53