Mathematical Backgrounds of Computer and Control System Reliability

Graph methods for recognition of CMOS gates in transistor-level circuits

D. I. Cheremisinov, L. D. Cheremisinova

The United Institute of Informatics Problems of the National Academy of Sciences of Belarus, Minsk, Belarus

Abstract: The paper focuses on the decompilation of a flat transistor circuit in SPICE format into a hierarchical network of logic gates. The problem arises in VLSI layout verification as well as in reverse engineering transistor circuit to redesign integrated circuit and to detect untrusted attachments. The most general case is considered when the extraction of functional level structure from transistor-level circuit is performed without any predetermined cell library. Graph methods for solving some key tasks in this area are proposed. The presented graph methods have been implemented in C++ as a part of a decompilation program, which has been tested using practical transistor-level circuits.

Keywords: CMOS transistor circuit, subcircuit extraction, logic gate recognition, graph isomorphism, SPICE format.

UDC: 681.32

Language: English

DOI: 10.17223/20710410/64/4