Circuits and Systems for Receiving, Transmitting and Signal Processing

SUB-6 GHz IP blocks for 5G transceivers in 65 nm CMOS

I. A. Rumyancev

Peter the Great St. Petersburg Polytechnic University

Abstract: This paper presents the development results of a vector modulator, a low-noise amplifier and a power amplifier for the 4.80–4.99 GHz. It is planned to deploy fifth-generation communication systems in this frequency band in the Russian Federation. Circuits, layouts and simulation results of the designed IP blocks are presented and compared with state-of-the-art works. All circuits are inductorless to improve bandwidth and reduce the layout area. Thus, the vector modulator area, which has the largest dimensions, is only 0.4 sq. mm. The use of a vector modulator that combines the functions of an attenuator and a phase shifter in the transceiver modules makes it possible to calibrate the amplitude-phase states to minimize the influence of the technological process parameters variation. According to the simulations results, the designed IP blocks allow implementing the transceiver for the whole sub-6 GHz band (3–5 GHz).

Keywords: vector modulator, power amplifier, low noise amplifier, CMOS, calibration, 5G.

UDC: 621.396.6

Received: 19.12.2020

Language: English

DOI: 10.18721/JCSTCS.13404