COMPUTING AND SOFTWARE SYSTEMS

Embedded test and debug system with JTAG interface for CMOS digital IC

M. S. Ladnushkin

Institute for System Research, Russian Academy of Sciences

Abstract: Proposed test and debug system based on scan technology for CMOS digital IC. Designed debug system makes a “snapshot” of logic states of all triggers in VLSI and provides transfer of test data to tester by JTAG. Proposed debug structure is low-area (0.2% overhead) which is 0.1% lower than compared system.

Keywords: VLSI debug, JTAG, design-for-debug.