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Ferroelectricity

Degradation of the SrRuO$_3$/SrTiO$_3$ interface capacitance induced by mechanical stresses

Yu. A. Boikov^a, T. Claeson<sup>b

a</sup> Ioffe Institute, St. Petersburg
^b Chalmers University of Technology, Göteborg, 412 58, Sweden

Abstract: Trilayer epitaxial heterostructures in which a 700-nm-thick SrTiO$_3$ interlayer is integrated with two SrRuO$_3$ electrodes have been grown by laser ablation. In the top electrode, twenty contact pads ($S\approx$ 0.1 mm$^2$) have been formed using photolithography and ion etching. The bottom SrRuO$_3$ electrode grown on a MgO(001) substrate is common for all film capacitors on the chip. As the temperature decreases in the range of 300–50 K, the capacitance $C$ of the capacitors increases by a factor more than two due to an increase in the permittivity $\varepsilon$ of the interlayer. At $T$ = 4.2 K, as the bias voltage of $\pm$ 2.5 V is applied to the oxide electrodes, the capacitance $C$ decreases by $\sim$40%. In the temperature range of 100–300 K, the ratio $\varepsilon_0/\varepsilon$ increases almost linearly with increasing temperature ($\varepsilon_0$ is the permittivity in vacuum). At $T >$ 250 K, the dielectric loss tangent of the SrTiO$_3$ interlayer increases exponentially with increasing temperature and substantially depends on the bias voltage applied to the oxide electrodes.

Received: 14.05.2014

 English version: Physics of the Solid State, 2014, 56:12, 2446–2450

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