Abstract:
The paper proposes a method for conversion of an arbitrary programmable logical matrix (PLM) to a checkable form and a method whereby for the resultant PLM a «short» test is obtained which checks all single faults such as transistor absence and arrival and all multiple faults composed of these single ones. The PLMs are converted by using the unconnected input and output polls. The upperbound of the number of poles sufficient for this conversion is provided PLMs of combinational logic and a PLM with memory are discussed.
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