This article is cited in 2 papers

Safety, Viability, Reliability, Technical Diagnostics

Project verification and construction of superchip tests at the RTL level

L. A. Zolotorevich

Belarus State University, Minsk, Belarus

Abstract: Methods were proposed for project verification and directed design of the superchip tests represented in VHDL at the RTL level. The problem of test design and project verification was solved on the basis of the CNF-satisfiability of some system of Boolean functions.

Presented by the member of Editorial Board: P. P. Parkhomenko

Received: 24.01.2012

 English version: Automation and Remote Control, 2013, 74:1, 113–122

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